1. Field of the Invention
The present invention relates to a timing analyzing system that examines a delay of an LSI having a clock path including a clock mesh structure.
2. Description of Related Art
As a clock distribution system for an LSI, a clock tree system is known. The clock tree system is a technique for distributing a clock signal in a tree structure. FIG. 1 is a circuit diagram illustrating a configuration of an LSI in which a clock signal is distributed in the clock tree system. In the LSI of FIG. 1, a circuit is preferably designed such that a difference in arrival time (skew) of the clock signal is minimized. Japanese Patent Application Publication (JP-A-Heisei 11-232310: first conventional example) describes a technique related to an integrated circuit design supporting apparatus that uses a wiring load model, in which an arrangement extension (distance) of a logic unit is taken into consideration, and generates an optimized logic circuit. Also, Japanese Patent Application Publication (JP-P2007-078536A: second conventional example) describes a technique that simplifies a net list by integrating two or more elements into one element.
For the preferable circuit design, in the LSI of the clock tree system, a SKEW calculation in which a manufacturing variation is taken into account is performed. In general, in the LSI of the clock tree system, as an arrangement extension (distance) increases, a delay variation increases, and as the number of stages increases, the delay variation decreases. On the other hand, as the arrangement extension (distance) decreases, the delay variation decreases, and as the number of stages decreases, the delay variation increases. There is such a correlationship, and therefore, in a static timing analysis (STA) tool, a delay variation coefficient is determined from a 2-dimensional table (library) between the arrangement extension (distance) and the number of stages, and the following expression is used to model the SKEW calculation.
Setup Skew:(transmission clock delay)−(variation coefficient(<1.0))×(reception clock delay)
Hold Skew:(transmission clock delay)−(variation coefficient(>1.0))×(reception clock delay)In this case, regarding the SKEW calculation obtained by taking a manufacturing variation into account, a common path to a transmission clock signal and a reception clock signal is recognized, and an arrangement extension (distance) of clock drivers subsequent to the common path is taken into account. In the clock common path, it is not necessary to consider any variation. For this reason, the arrangement extension, the number of stages, and clock delay after a common path branch point (hereinafter, to be described as a CRPR (Clock Reconvergence Pessimism Removal) branch point) are calculated.
For example, if a clock signal on a path between a first flip-flop FF1 and a second flip-flop FF2 is “uniquely” traced upstream, a path up to a first CRPR branch point can be recognized as a common path. Also, between the first flip-flop FF1 and the second flip-flop FF2, the number of stages is one, and an arrangement extension is a first range. If a clock signal on a path between the first flip-flop FF1 and a third flip-flop FF3 is “uniquely” traced upstream, a path up to a second CRPR branch point can be recognized as a common path. Also, between the first flip-flop FF1 and the third flip-flop FF3, the number of stages is three, and an arrangement extension is a second range.
The clock tree system has a high degree of freedom of a layout design. However, in a large-scale circuit, there may be a case where it is difficult to reduce a difference in arrival time (skew) of a clock signal. As a clock distribution system that reduces the skew in the LSI having a large circuit scale, a clock mesh system is known in conventional techniques such as Japanese Patent Application Publications (JP-A-Heisei 03-232267: third conventional example, JP-P2003-282712A: fourth conventional example). The clock mesh system can reduce a clock delay variation due to a manufacturing variation within a chip, and reduce a skew even for a large-scale circuit. For this reason, a high-end LSI using mesh architecture as a clock structure has become widely used. FIG. 2 is a circuit diagram illustrating a configuration of an LSI of the clock mesh system. Referring to FIG. 2, in the LSI, a clock signal is distributed in a grid (mesh) structure.
As illustrated in the FIG. 1, in the typical clock tree distribution, a data line typically has a single driver configuration except for a bus, and if a fan-in (driver) side of a net or cell is traced, a unique cell is inevitably reached. On the other hand, if there is a mesh structure in a clock path, a common path cannot be recognized, and therefore an accurate arrangement extension cannot be specified. In the clock mesh structure, if a fan-in side is traced, a driver is not uniquely determined, and therefore a special algorithm or consideration on a program is required. As described, the clock mesh structure should have a multi-driver configuration, and is therefore difficult to handle with a general CAD tool.
The static timing analysis (STA) tool is also no exception. In an LSI as illustrated in FIG. 2, there is no tool that calculates a delay variation in a mesh section due to a manufacturing variation within a chip. Accordingly, it may be difficult to perform a highly accurate timing analysis with a calculation model reflecting the manufacturing variation. For example, a method is considered that uses a delay measured by a Monte Carlo SPICE simulation analysis in which a portion from a PLL to a mesh stage is extracted as a netlist of a transistor level, and manufacturing variations in a wiring medium and a transistor are used as random factors. However, this is not practice use in view of an execution time.